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To reorder instructions to exploit instruction slots available after delayed branch instructions. When the branch behaves as predicted, the instruction in the branch delay slot is simply executed as it would normally be with a delayed branch. When the branch is incorrectly predicted, the instruction in the branch delay slot is simply turned into a no-op. Examples of such branches are cancel-if-taken or cancel-if-not-taken branches. That is like what happens with a branch, somewhere deep in the assembly line, something causes the line to have to change, dump the line. The delay slot is a way to recover one product from having to be discarded in the line. Instead of n products coming out before the line stopped, n+1 products came out per production run. The interrupt handler can't return to the delay slot because then it wouldn't see the branch at all, so it would fall through on exception return even if the branch condition was true. Branch delay slots are a bad idea conceptually, and small numbers of branch delay slots are also useless on microarchitectures with long pipelines. Re-execute the *beq a0, zero, _true* and the branch delay will be a nop so it will have no effect. Place a sw breakpoint at the target (s) of the branch and set a flag. Once the sw breakpoint is hit restore the branch delay slot and remove traces of the sw breakpoints. When an exception occurs, the processor captures the address of the faulting instruction into a special control register called epc (exception program counter), and the value of in_branch_delay_slot is captured into a special control flag called bd (branch delay)
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Eliminating the branch stall • there’s no rule that says we have to see the effect of the branch immediately. Why not wait an extra instruction before branching? • the original sparc and mips processors each used a single branch delay slot to eliminate single-cycle stalls after branches. Specifically what happens in on a cpu implementing release 6 of the mips32 isa is the following: if status. Exl == 0 then: if syscall instruction in a branch delay slot: epc = pc – 4. Badinstr = memory [pc] badinstrp = memory [pc – 4] if syscall instruction not in a branch delay slot: epc = pc. The problem gives two hints: it reminds us that branches and jumps are delayed and need their delay slots filled in and it hints at chaging the offset value in memory accesss instructions (lw,sw) when necessary. Loop: lw $1, 100 ($2) addi $1, $1, 1 sw $1, 500 ($2) addiu $2, $2, 4 bne $2, $10, loop. By convention, if an exception or interrupt prevents the completion of an instruction in the branch delay slot, the instruction stream is continued by re-executing the branch instruction. There are a few ways to implement this in a classic 5-stage risc in general. For unconditional direct (not register) branches, obviously you can detect them in id and have the target pc ready for the next if cycle (with 1 cycle of branch latency, i. 1 wasted if cycle if you don't hide that latency somehow, e. Mips's branch delay slot or branch prediction). When an exception occurs, the processor captures the address of the faulting instruction into a special control register called epc (exception program counter), and the value of in_branch_delay_slot is captured into a special control flag called bd (branch delay)
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